Power consumption of electronic devices that include integrated circuitry is increasingly becoming an important issue for any one or more of a number of reasons. For example, as the operating speeds of integrated circuits (ICs) continually increase, in general so, too, do the power requirements for these circuits, since power consumption varies in direct relation to the operating speed. In addition, as each new generation of technology brings a decrease in feature size and an increase in integration scale, power consumption of ICs generally increases due to the sheer presence of many more circuit elements, e.g., transistors and the like. Furthermore, with the increasing integration scale, electronic devices are capable of supporting more and more features. Power consumption typically increases with greater numbers of features, particularly when a feature requires circuitry that would not be needed in the absence of that feature.
While power consumption of ICs is becoming increasingly important regardless of whether the power source for an IC is portable, such as a battery or fuel cell, or non-portable, such as a power utility distribution network, power consumption is presently more critical in the context of portable power sources, which generally lag ICs in term of performance. For example, state-of-the-art lithium-ion and nickel-cadmium batteries can store only enough energy to power portable, or mobile, electronic devices, e.g., current-generation laptop computers and cell phones, typically for about two to five hours at full power before the batteries need to be recharged. While such operating times represent an improvement over previous-generation batteries, they are much shorter than most consumers would like.
There are a number of conventional methods for reducing power consumption of ICs. One method is to simply reduce the systemic operating voltage of the IC. While this method has the ability to significantly reduce the power consumption of ICs (e.g., reducing the operating voltage from 5V to 3.3V results in a gross power reduction of about 56%), there are practical limits to this method. Another method of reducing power consumption of ICs is to reduce the amount of logic circuitry. There are clearly practical limits to this method as well. Consequently, one, the other or both of these methods are typically used in connection with one or more power management methods that seek to reduce the power provided to portions, or “functional blocks,” of ICs during periods when these blocks are not needed.
Generally, conventional power management methods involve dynamic scaling of voltage, frequency or both. In the context of integrated systems, such as a Systems On Chips (SOCs), that utilize standardized bus architectures and standardized functional blocks, e.g., standardized macros and peripherals, frequency scaling is particularly problematic. This is so because if the operating frequency is slowed to a point below the natural sampling rate of the transceivers, system data is lost. A solution to this data loss would be to redesign the transceivers to provide asynchronous message passing and allow the transceivers to be asynchronous to the bus architecture. Drawbacks of this solution are that it would be relatively costly and inherently risky in terms of system lockup potential when implemented with standardized bus interfaces that are designed to be synchronous to a system master.